1. Field of the Invention
The present invention relates to a substrate of a semiconductor integrated circuit, and more particularly to a substrate on which a semiconductor integrated circuit is to be formed, the semiconductor integrated circuit comprising a plurality of circuit sections, each of the circuit sections having a different kind of resistance to which great importance is attached because of different functions of the circuit sections, for example, a circuit section formed by using a plurality of transistors, a circuit section having a lot of storage capacitors of a DRAM formed thereon, and the like.
2. Description of the Background Art
FIG. 45 is a plan view showing a relationship between a wafer and a substrate of a semiconductor integrated circuit. Independent semiconductor integrated circuits are formed on a plurality of regions 2 in a wafer 1, respectively. Examples of the semiconductor integrated circuit include a semiconductor memory. By taking the semiconductor memory as an example, the prior art related to the substrate of the semiconductor integrated circuit will be described below.
Conventionally, soft error, latch up and electro-static discharge (hereinafter referred to as ESD) have mainly been known as the causes of a malfunction of a memory cell forming the semiconductor memory. In this order, phenomena will briefly be described below. The prior art which has been carried out as countermeasures will be described below.
The soft error means a temporary malfunction which is randomly generated in an integrated circuit due to a passage of xcex1-rays through the integrated circuit and can be recovered. The xcex1-rays are emitted from uranium (U) and thorium (Th) contained in a small quantity in a package housing the integrated circuit, an aluminum wiring to be used for manufacturing the integrated circuit, a silicide electrode, and the like. xcex1-particles are charged to positive bivalence by an atomic nucleus of helium (He++). When the xcex1-particle passes through the integrated circuit, an electron-hole pair having a concentration of 1017 to 1020cm3 is generated. The generated electrons or holes to act as minority carriers flow into a p-type diffusion layer or an n-type diffusion layer to change electric charges stored in the diffusion layer. For this reason, the temporary malfunction, that is, the soft error is caused.
Whether the soft error is actually caused or not greatly depends on how the minority carriers of the generated electron-hole pairs are collected into the diffusion layer in addition to the generation of the electron-hole pairs. As the process of causing the soft error, the following three mechanism are given. Small pieces of a semiconductor on which individual integrated circuits are formed will be hereinafter referred to as substrates.
(1) Drift of the minority carriers in a depletion layer.
(2) Diffusion of the minority carriers on a neutral region in the substrate.
(3) A funneling effect in which an electric field generated by flow of majority carriers accelerates collection of the minority carriers into the diffusion layer.
(1) indicates a mechanism in which the minority carriers generated by xcex1-rays incident on the depletion layer are collected into the diffusion layer by an electric field for drift which is applied to the depletion layer. A time taken for carrier collection is approximately an order of 10xe2x88x9211 second. On the other hand, there is the Auger process as a carrier recombination process in a silicon substrate which is doped at a high concentration. A lifetime of the minority carrier depends on an impurity concentration of the diffusion layer. The lifetime of the electron ranges from 3xc3x9710xe2x88x925 second (hole concentration: 1016/cm3) to 1xc3x9710xe2x88x929 second (hole concentration: 1020/cm3). The lifetime of the hole ranges from 1xc3x9710xe2x88x925 second (electron concentration: 1016/cm3) to 4xc3x9710xe2x88x9210 second (electron concentration: 1020/cm3). A time taken for the carrier collection performed by the electric field for drift is approximately an order of 10xe2x88x9211 second. Therefore, it is apparent that the carrier collection is seldom affected by recombination.
(2) indicates a mechanism in which the minority carriers in the neutral region are collected into the diffusion layer by diffusion. A diffusion coefficient Dn of the electron is 10 to 30 cm2/sec. A lifetime xcfx84 n of the electron ranges 3xc3x9710xe2x88x925 to 1xc3x9710xe2x88x929 second. An average diffusion length 1 d of the electron is given by a square root of a product of the diffusion coefficient Dn and lifetime xcfx84 n of the electron.
The average diffusion length 1 d thus obtained ranges from 1 xcexcm (hole concentration: 1020/cm3) to 300 xcexcm (hole concentration: 1016/cm3). An energy of xcex1-particles emitted from uranium and thorium often ranges from 4 MeV to 5 MeV. A range of the xcex1-particles having an injection energy of 5 MeV is about 23 xcexcm. Accordingly, if a boron concentration of a p-type substrate is 1016/cm3, the electrons generated by the xcex1-particles are collected into the diffusion layer by diffusion. If the boron concentration of the p-type substrate is 1020/cm3, most of the electrons generated by the xcex1-particles in a portion which is deeper than the diffusion layer by 1 xcexcm or more are recombined and are not collected by the diffusions.
Next, description will be given to the mechanism (3) wherein the minority carriers are collected into the diffusion layer by the funneling effect in which the electric field generated by the flow of the majority carriers accelerates the collection of the minority carriers into the diffusion layer. If the electron-hole pairs generated by the xcex1-particles are separated by the electric field applied into the depletion layer, a dipole electric field is generated by the separated electrons and holes. The dipole electric field weakens the electric field which has been applied into the depletion layer. Therefore, a part of the depletion layer deeply enters the substrate so that a voltage drop is caused. Due to the electric field deeply entering the substrate, the minority carriers generated in the substrate by the xcex1-particles are collected into the diffusion layer formed on a surface of the substrate.
Various well structures have conventionally been proposed in order to prevent the soft error from being caused by the xcex1-particles. A high concentration impurity layer acting as a barrier to the minority carriers has been formed in such a manner that the minority carriers generated in the substrate do not reach the integrated circuit formed in the vicinity of the surface of the substrate of the semiconductor integrated circuit. The high concentration impurity layer has been formed by performing heat treatment after ions are implanted at a high energy. According to this method, a thickness of the impurity layer is insufficient. Therefore, epitaxial wafers such as a p on pxe2x88x92 wafer, a p on p+ wafer, a p on p++ wafer and the like have recently been used as substrate materials. Each of the substrates formed on the epitaxial wafers (which will be hereinafter referred to as a p on pxe2x88x92 substrate, a p on p+ substrate and a p on p++ substrate, respectively) includes a semiconductor surface layer which is subjected to epitaxial growth on a substrate single crystal of the semiconductor cut out of an ingot, and the semiconductor substrates have impurity concentrations of pxe2x88x92, p+ and p++. A structure of a substrate of a semiconductor integrated circuit formed by using these wafers will be described below with reference to FIG. 39.
FIG. 39 is a typical diagram showing a sectional structure of the p on pxe2x88x92 substrate, the p on p+ substrate or the p on p++ substrate according to the prior art. An epitaxial layer 101 which is a p-type semiconductor surface layer is formed on a substrate single crystal 102 which is a p-type semiconductor substrate layer. In this specification, the semiconductor surface layer is a layer made of a single crystal having a single orientation which is provided on a surface of a semiconductor substrate and on which an integrated circuit is formed. The semiconductor substrate layer is made of a single crystal which serves to become a direct growth origin of the semiconductor surface layer and to determine the orientation of the semiconductor surface layer. The semiconductor surface layer is a layer having an almost uniform impurity concentration such as an epitaxial layer or a substrate single crystal of a wafer, and is different from a layer (a well or the like) to which an impurity is added after a crystal is formed by diffusion or the like.
The p on pxe2x88x92 substrate, the p on p+ substrate and the p on p++ substrate are different from one another in that the p-type substrate single crystal has different impurity concentrations. The following division of the impurity concentration is convenient but is not general, and is defined on the basis of a relationship with the effects of the present invention. The impurity concentration of each substrate single crystal is equal to or greater than 1015/cm3 and is smaller than 1018/cm3 on the pxe2x88x92 layer, is equal to or greater than 1018/cm3 and is smaller than 1020/cm3 on the p+ layer, and is equal to or greater than 1020/cm3 on the p++ layer.
By using these substrate structures, a layer acting as a barrier to the electrons is provided in a lower portion of the semiconductor substrate layer, that is, a lower portion of the epitaxial layer. Therefore, it is expected that a soft error resistance is increased. However, the soft error resistance is not actually increased. The reason is that electric charges collected into the diffusion layer are almost equal to electric charges collected by funneling. This means that the minority carriers generated by the xcex1-particles are collected into the diffusion layer by the funneling for a shorter time than a time for which they decay by the Auger recombination in the high concentration impurity layer. Accordingly, even if the p on p+ substrate and the p on p++ substrate are used, effects of the decay of the generated minority carriers caused by the Auger recombination cannot be expected. For this reason, it is impossible to decrease the electric charges collected into the diffusion layer.
If a thickness of the semiconductor surface layer is equal, fewer electric charges are collected into the diffusion layer of the substrate surface on the p on pxe2x88x92 substrate where the minority carriers easily escape to a back side than the p on p+ substrate. This means that the p+ layer provided under the semiconductor surface layer acts as the barrier both in a direction of the substrate surface and that of the back side in respect of the minority carriers. The electrons easily escape to the back side because a potential barrier layer is lower on the pxe2x88x92 layer than the p+ layer. Therefore, the p on pxe2x88x92 wafer has a greater soft error resistance than the p on p+ wafer. From the above-mentioned consideration, it is apparent that the p on pxe2x88x92 substrate is effective in the soft error if a difference in a defect density is ignored.
Next, the latch up which is the second cause of the malfunction of the semiconductor memory cell will be described. The latch up means a malfunction of a CMOS device which is caused by operation of a thyristor that can be fabricated by parasitism when the CMOS device is formed on a surface of a substrate.
With reference to FIG. 40, a mechanism of the latch up will be described below. FIG. 40 is a typical diagram showing an example of a sectional structure of a CMOS transistor. In the CMOS transistor shown in FIG. 40, an n well 104 is provided on a p-type substrate 103 to isolate adjacent transistors having different conductivity types from each other. It is apparent that such a CMOS transistor includes a lateral type npn parasitic bipolar transistor Q1 and a vertical type pnp parasitic bipolar transistor Q2. FIG. 41 shows an equivalent circuit of a parasitic circuit formed with this structure. RP1 and RP2 represent resistances generated on the p-type substrate 103, and RN1 and RN2 represent resistances generated on the n well 104. The parasitic circuit formed by the two parasitic bipolar transistors Q1 and Q2 and the resistances RP1, RP2, RN1 and RN2 causes the latch up. As the cause of the latch up, overshoot and undershoot of voltages VIN and VOUT on an input terminal 105 and an output terminal 106, internal punch through and avalanche multiplication, a leak current of a parasitic MOS transistor and the like are given. The overshoot and undershoot of the voltages VIN and VOUT on the input terminal 105 and the output terminal 106 will be described below.
With reference to FIG. 42, description will be given to operation of the CMOS transistor which is performed when the voltage of the output terminal 106 is overshot. Usually, a supply voltage VDD is applied from a power terminal 108 to the n well 104, and a ground voltage VSS is applied from a ground terminal 107 to the p-type substrate 103. If the voltage VOUT of the output terminal 106 is raised to the supply voltage VDD or more (overshoot) due to some cause in this state, a pn junction of a p+ region connected to the output terminal 106 and the n well 104 is forward biased. Consequently, a large number of holes are injected from the p+ region toward the n well 104. The pn junction formed by the n well 104 and the p-type substrate 103 is reversely biased. Therefore, the holes are collected into the PN junction and flow into the p-type substrate 103, thereby being changed into a majority carrier current. Since the majority carrier current flows into the ground terminal 107 provided on the surface or back side of the p-type substrate 103, it causes an ohmic voltage drop in the p-type substrate 103. As a result, an emitter-base of a lateral type parasitic bipolar transistor comprising an n+ region connected to the ground terminal 107, the p-type substrate 103 and the n well 104 is forward biased so that the lateral type transistor is conducted. An electronic current flowing in the lateral type transistor is changed into a majority carrier in the n well 104 to cause the ohmic voltage drop. Consequently, a base-emitter of a vertical type bipolar transistor is forward biased increasingly. If positive feedback is fully increased, the latch up is caused so that a great current flows from the output terminal 106 toward the ground terminal 107.
If the voltage of the output terminal 106 is undershot, the equivalent circuit is changed as shown in FIG. 43. A basic mechanism is the same as in the case of the above-mentioned overshoot except that carriers to be injected into bases of the two parasitic bipolar transistors Q1 and Q2 are electrons.
In brief, collector currents of the two parasitic bipolar transistors Q1 and Q2 in the CMOS device flow in the resistances RN1 and RP1 provided between mutual emitters and bases respectively so that the emitters and the bases are forward biased, thereby causing the latch up.
As is apparent from the above-mentioned consideration, a reduction in an ohmic voltage drop in the p-type substrate 103 or in the n well 104 is effective in prevention of the latch up. It is found that a deep portion of the p-type substrate 103 is formed by a p+ layer and a p++ layer, that is, the p on p+ substrate and the p on p++ substrate have structures which are effective in the latch up.
Next, the ESD (Electro-Static Discharge) which is the third cause of the malfunction of the semiconductor memory cell will be described with reference to FIG. 44. In some cases, a pxe2x88x92 semiconductor surface layer 111 is formed on a p-type substrate 110 having a high impurity concentration and an element 112 is formed on the semiconductor surface layer 111 in order to prevent undershoot of a voltage on an input terminal. An external circuit 113 connected to the semiconductor substrate 110 shown in FIG. 44 is an equivalent circuit of a human body with the human body coming in contact with an input-output terminal 114 of a chip. According to a simulation, in the case where the epitaxial substrate 110 using an epitaxial wafer is utilized, an ESD resistance is reduced more than in a substrate using a wafer manufactured by the Czochralski method (which will be hereinafter referred to as a CZ substrate). A reduction in the ESD resistance is caused by the following fact. A substrate resistance Rsub of the epitaxial substrate 110 is lower than in the CZ substrate. Therefore, the parasitic bipolar transistor (npn lateral type) operates with difficulty and a voltage of an electrode is held at a higher value. The voltage of the electrode is held high so that an electric field in the element is increased and a lattice temperature is raised. When the lattice temperature is higher than a melting point of the semiconductor substrate 110, the element is molten and broken. Accordingly, it is apparent that the p on pxe2x88x92 substrate is better than the p on p+ substrate from the viewpoint of the ESD resistance.
The three causes of the malfunction of the integrated circuit, that is, the soft error, the latch up and the ESD have been described above. Table 1 shows a substrate structure which is effective in prevention of respective phenomena.
It is desirable that a single substrate structure should be effective in the prevention of all the above-mentioned phenomena. It is apparent from Table 1 that any substrate structure cannot simultaneously prevent all the phenomena of the soft error, the latch up and the ESD.
Recently, an epitaxial wafer having an epitaxial layer for forming the p on p+ substrate, the p on pxe2x88x92 substrate and the like has been used for mass production of an integrated circuit rather than the CZ substrate for two other reasons in addition to the fact that the epitaxial wafer serves to suppress the above-mentioned three malfunctions. The first reason is that a breakdown voltage of a thermal oxide film is high because the epitaxial wafer has a smaller micro defect density of crystal originated-particles (hereinafter referred to as COP), flow pattern defects (hereinafter referred to as FPD) or the like which highly correlate with the breakdown voltage of the thermal oxide film as compared with the CZ wafer. It has been found that the breakdown voltage of the thermal oxide film checked by way of a non-defective rate is increased if the density of the COP or the FPD is reduced. The second reason is as follows. While the use of a wafer having a bore of 300 mm is indispensable to an increase in payability in mass-produced integrated circuits, it is hard to fabricate a CZ wafer having a bore of 300 mm and a smaller defect density of the COP or the FPD. In addition, a cost is increased more than in the epitaxial wafer. In other words, it can be concluded that the epitaxial wafer is more excellent than the CZ wafer with a great bore of 300 mm or more in respect of the quality and cost.
As described above, in the semiconductor memory device manufactured by using a substrate of a semiconductor integrated circuit and an integrated circuit on which a memory and a logic are mounted together according to the prior art, the circuit portions which attach great importance to resistances to different phenomena, for example, the memory cell section, the logic section, the input-output section and the like are formed on a single substrate. Therefore, there has been a problem that it is not easy to simultaneously obtain desirable resistances to all the different phenomena such as the soft error, the latch up, the ESD and the like even if any of the p on pxe2x88x92 structure, the p on p+ structure and the p on p++ structure is employed as a structure of the substrate of the semiconductor integrated circuit.
A first aspect of the present invention is directed to a substrate of a semiconductor integrated circuit comprising a first semiconductor substrate layer made of a substrate single crystal having a single orientation and having a first impurity concentration almost uniformly thereover, a second semiconductor substrate layer formed on the first semiconductor substrate layer and made of a single crystal having the same orientation as that of the first semiconductor substrate layer, having a second impurity concentration, and having the same conductivity type as that of the first semiconductor substrate layer, a first semiconductor surface layer directly formed on the first semiconductor substrate layer and made of a single crystal having the same orientation as that of the first semiconductor substrate layer, having a third impurity concentration almost uniformly thereover and having the same conductivity type as that of the first semiconductor substrate layer for forming a first circuit section including a plurality of semiconductor elements, and a second semiconductor surface layer directly formed on the second semiconductor substrate layer and made of a single crystal having the same orientation as that of the second semiconductor substrate layer, having a fourth impurity concentration almost uniformly thereover and having the same conductivity type as that of the second semiconductor substrate layer for forming a second circuit section including a plurality of semiconductor elements and having a function which is different from that of the first circuit section, wherein the first impurity concentration is different from the second impurity concentration.
A second aspect of the present invention is directed to the substrate of a semiconductor integrated circuit according to the first aspect of the present invention, wherein the first semiconductor surface layer is an epitaxial layer of an epitaxial wafer, and the first semiconductor substrate layer is a substrate single crystal of the epitaxial wafer.
A third aspect of the present invention is directed to the substrate of a semiconductor integrated circuit according to the second aspect of the present invention, wherein the second semiconductor substrate layer and the second semiconductor surface layer are formed on a trench provided on the epitaxial wafer, and the second semiconductor substrate layer is an epitaxial layer.
A fourth aspect, of the present invention is directed to a substrate of a semiconductor integrated circuit comprising a first semiconductor surface layer made of a single crystal having a single orientation and having an almost uniform first impurity concentration thereover for forming a first circuit section including a plurality of semiconductor elements, a second semiconductor surface layer made of a single crystal having the same orientation as that of the first semiconductor surface layer, having the same conductivity type as that of the first semiconductor surface layer and having an almost uniform second impurity concentration thereover for forming a second circuit section including a plurality of semiconductor elements and having a function which is different from that of the first circuit section, and a semiconductor substrate layer which is made of a substrate single crystal having the same orientation as that of each of the first and second semiconductor surface layers, having the same conductivity type as that of each of the first and second semiconductor surface layers and further having an almost uniform third impurity concentration thereover to act as a formation substrate of each of the first and second semiconductor surface layers, and which has first and second principal planes whose heights are different from each other, wherein the first semiconductor surface layer is directly formed on the first principal plane, the second semiconductor surface layer is directly formed on the second principal plane, and the third impurity concentration is different from both the first and second impurity concentrations.
A fifth aspect of the present invention is directed to the substrate of a semiconductor integrated circuit according to the fourth aspect of the present invention, wherein the first semiconductor surface layer is an epitaxial layer of an epitaxial wafer, and the first semiconductor substrate layer is a substrate single crystal of the epitaxial wafer.
A sixth aspect of the present invention is directed to the substrate of a semiconductor integrated circuit according to the fifth aspect of the present invention, wherein the second principal plane is a bottom face of a trench dug over the epitaxial layer of the epitaxial wafer.
A seventh aspect of the present invention is directed to the substrate of a semiconductor integrated circuit according to the fifth aspect of the present invention, wherein the second principal plane is a top face of an epitaxial layer which is newly formed on a bottom face of a trench dug over a surface of the epitaxial wafer.
An eighth aspect of the present invention is directed to the substrate of a semiconductor integrated circuit according to any of the first to seventh aspects of the present invention, further comprising an alignment mark for specifying places where the first circuit section and the second circuit section are to be formed.
A ninth aspect of the present invention is directed to the substrate of a semiconductor integrated circuit according to any of the first to eighth aspects of the present invention, wherein a heavy metal is diffused into a region having a predetermined depth from the first or second semiconductor surface layer.
A tenth aspect of the present invention is directed to a substrate of a semiconductor integrated circuit comprising a semiconductor substrate layer made of a single crystal having a single orientation and having a first impurity concentration almost uniformly thereover, and a semiconductor surface layer directly formed on the semiconductor substrate layer and made of a single crystal which has the same conductivity type and orientation as those of the semiconductor substrate layer and has a well, wherein the semiconductor surface layer includes a predetermined partial region interposed between the well and the semiconductor substrate layer, and the predetermined partial region has a second impurity concentration which is lower than the first impurity concentration and is the lowest in the semiconductor surface layer, and has a thickness of about 2 xcexcm or more.
An eleventh aspect of the present invention is directed to a method for manufacturing a semiconductor integrated circuit, comprising the steps of preparing an epitaxial wafer having a substrate single crystal, a first epitaxial layer directly formed on the substrate single crystal, and an insulation film formed on the first epitaxial layer, forming, on the epitaxial wafer, a trench and a pit whose openings have different sizes from each other, forming a second epitaxial layer on the trench and the pit in such a thickness as not to fill in the trench and the pit, forming a third epitaxial layer over the epitaxial wafer in such a thickness as to fill in the trench and not to fill in the pit, removing a portion of the third epitaxial layer provided outside the trench and the pit, and flattening a surface of the third epitaxial layer to almost align with a surface of the first epitaxial layer, and forming a semiconductor integrated circuit on the basis of the pit.
According to the first aspect of the present invention, the impurity concentration of the first semiconductor substrate layer of the first circuit section is made different from that of the second semiconductor substrate layer of the second circuit section. Consequently, structures advantageous to resistances which are demanded for different phenomena in the first and second circuit sections in the substrate of the semiconductor integrated circuit can independently be provided in the first and second circuit sections, and desirable resistances can easily be obtained simultaneously for all the different phenomena over the whole substrate of the semiconductor integrated circuit. Furthermore, the impurity concentrations of the first and second semiconductor substrate layers are almost uniform over the layer. Therefore, even if the substrate includes a lot of elements forming the first and second circuit sections, each element can easily have an expected performance.
According to the second aspect of the present invention, the existing epitaxial wafer is used. Consequently, a lot of time and labor required to form the first semiconductor surface layer on the first semiconductor substrate layer can be saved. Thus, a desirable substrate can easily be fabricated.
According to the third aspect of the present invention, the second semiconductor substrate layer and the second semiconductor surface layer can be formed on the first semiconductor substrate layer, and the first and second semiconductor surface layers can easily be integrated.
According to the fourth aspect of the present invention, the thickness of the semiconductor surface layer provided under the first circuit section is made different from that of the semiconductor surface layer provided under the second circuit section. Consequently, thicknesses advantageous to resistances demanded for different phenomena can independently be set in the first and second circuit sections, and desirable resistances can easily be obtained simiultaneously for all the different phenomena over the whole substrate of the semiconductor integrated circuit.
According to the fifth aspect of the present invention, the existing epitaxial wafer is used. Consequently, a lot of time and labor required to form the first semiconductor surface layer on the semiconductor substrate layer can be saved. Thus, a desirable substrate can easily be fabricated.
According to the sixth aspect of the present invention, the second principal plane which is lower than the first principal plane can easily be obtained by the trench.
According to the seventh aspect of the present invention, the second principal plane which is higher than the first principal plane can easily be obtained by the third semiconductor surface layer.
According to the eighth aspect of the present invention, positions of the first and second circuit sections can be recognized by the alignment mark, and positions in which the first and second circuit sections are to be formed can be distinguished from each other by appearances to form an integrated circuit.
According to the ninth aspect of the present invention, a resistance to soft error can further be increased by the heavy metal.
According to the tenth aspect of the present invention, it is possible to obtain a practically sufficient soft error resistance in a storage capacitor which is formed on the substrate of the semiconductor integrated circuit and can store electric charges of about 18 fC to 20 fC, for example.
According to the eleventh aspect of the present invention, a place where the trench was formed can easily be specified on the basis of the pit, and the place where the trench was formed and other places can easily be distinguished to form a semiconductor integrated circuit.
In order to solve the above-mentioned problems, it is an object of the present invention to provide a substrate of a semiconductor integrated circuit which can easily manufacture a semiconductor memory device having a fully high resistances to all of soft error, latch up and ESD and a device on which a memory and a logic are mounted together.
It is another object of the present invention to enhance a soft error resistance also in a substrate of a semiconductor integrated circuit having a well.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.